Feedback Transimpedance Amplifier Design

Feedback Transimpedance Amplifier Design project requires LT spice .In this assignment, you will design a simple feedback network for a transimpedance amplifier. The goal is
to achieve an order of magnitude improvement in the bandwidth compared to the open-loop version of
the transimpedance amplifier. A transimpedance amplifier is designed as a common-source
stage as on the left. The design parameters are as follows: ??? =
5 ?, ????? = 3.9 ?, (
?
?
)
1
=
3.25 ??
1 ??
, (
?
?
)
2
=
10 ??
1 ??
, ?? = 100 ?,
??
‘ = 40 ??
?2
, ??
‘ = 120
??
?2
, ??? = 0.8 ?, ??? = -0.9 ?, ?? =
100 ?O, ???? = ???? = 1
??
?
.
1. For the values above, calculate
??1,??2, ??1, ??2,???1,???2, ??1, ??2, ??? ??????? ???? =
?? =
????
???
.
2. Simulate the circuit in LTSpice. Use nmos4 and pmos4
models. Connect nmos4 bulk to ground. Connect pmos4 bulk to
VDD. Refer to SPICE Assignment 2 document for entering W and L
values of the devices. Enter “.model pmos pmos (kp=40e-6, vt0=-
0.9, cgso=1n, cgdo=1n, lambda=0.01)” and “.model nmos nmos (kp=120e-6, vt0=0.8, cgso=1n,
cgdo=1n, lambda=0.01)” for remaining device parameters as shown below.
fall2017_spice_3.pdf

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EE 430 SPICE ASSIGNMENT #3
Feedback Transimpedance Amplifier Design
Due: Dec. 14, 2017.
In this assignment, you will design a simple feedback network for a transimpedance amplifier. The goal is
to achieve an order of magnitude improvement in the bandwidth compared to the open-loop version of
the transimpedance amplifier.
Part 1. Open-Loop Transimpedance Amplifier
A transimpedance amplifier is designed as a common-source
stage as on the left. The design parameters are as follows: ??? =
?
3.25 ?? ?
10 ??
, ( ? ) = 1 ?? , ?? = 100 ?,
1 ??
2
??
??
??’ = 40 ? 2 , ??’ = 120 ? 2 , ??? = 0.8 ?, ??? = -0.9 ?, ?? =
??
100 ?O, ???? = ???? = 1 .
?
5 ?, ????? = 3.9 ?, ( ? ) =
1
1.
For
the
values
above,
calculate
??1 , ??2 , ??1 , ??2 , ???1 , ???2 , ??1 , ??2 , ??? ??????? ???? =
?
?? = ????.
??
2.
Simulate the circuit in LTSpice. Use nmos4 and pmos4
models. Connect nmos4 bulk to ground. Connect pmos4 bulk to
VDD. Refer to SPICE Assignment 2 document for entering W and L
values of the devices. Enter “.model pmos pmos (kp=40e-6, vt0=0.9, cgso=1n, cgdo=1n, lambda=0.01)” and “.model nmos nmos (kp=120e-6, vt0=0.8, cgso=1n,
cgdo=1n, lambda=0.01)” for remaining device parameters as shown below.
a. Run a dc simulation (.op) to verify your hand calculations of ??1 , ??2 , ???1 , ???2 .
b. Set your input current signal to a 10 nA-peak and 1 Hz sinusoidal current with a dc value
of 10 µA: ??? = 10 ?? + 10 ?? * sin(2 * ? * 1 * ?) as shown on the next page. Run a five
seconds transient simulation (.tran) to verify your hand calculation of ??????? ???? =
?
?? = ????.
??
3. Do a hand calculation to estimate the bandwidth of the amplifier. ???? (??? = ???? *
????h ?? ?h? ??????) ??? (??? = ???? * ????h ?? ?h? ??????)
4. Run an (.ac) simulation. Before running the .ac simulation, make sure the current source has an
AC Amplitude of ‘1’ as shown above. Select “Decade” as the type of sweep and select 100 numbers
per decade with a start frequency: 1Hz and stop frequency: 1GHz. Provide the frequency response
of the output node in your report. On the plot, show the midband gain value and fH, Convert the
simulation midband gain, which is in [dB], into the gain unit of a transimpedance amplifier, which
is in [Ohms]. Compare simulation values with your hand calculations.
Part 2. Negative-Feedback Closed-Loop Amplifier
The circuit on the left is the same transimpedance
amplifier
in
negative-feedback
closed-loop
configuration using a feedback resistor, ?? , added
between the input and output nodes. In this part, use
the same circuit/device parameters as before.
1. Determine the feedback network (i.e.,
? ???????) and derive the expression for the
feedback network gain (?). Use your calculations in
Part 1 and ? to calculate a value for ?? such that
closed-loop bandwidth, ???? , is approximately an
order of magnitude greater than the open-loop
bandwidth, ???? (i.e., ???? = ~10 ? ???? ). For
the value you choose for ?? , what will be your
closed-loop gain (ACL)?
2. On your original LTSpice schematics, add the
closed-loop circuit above with the ?? value you
calculated. With both circuits (i.e., open-loop and
closed-loop amplifiers) up on the same schematics, run an (.ac) simulation. Plot the Bode Plots for
output voltages of both circuits. Compare your calculated and simulated ???? ??? ??? values.

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